OPNET Technologies
3400 International Drive, NW
Washington, DC 20008
Tel: 202-364-4700

Fax: 202-364-8554
E-mail: university@opnet.com
Web: www.opnet.com

OPNET is a registered
trademark of OPNET Technologies

© 2000 OPNET Technologies

University: New Jersey Institute of Technology
Constantin Manikopoulos
Department: Department of Electrical and Computer Engineering

1. A Hierarchical Traffic Shaper Implementation in High-Speed ATM Switches

Broadband networks must accommodate the diverse traffic parameter and quality-of-service (QoS) requirements of integrated services. In order to utilize network resources effectively while providing satisfactory quality of service (QoS) to all users on the ATM network, it is necessary to control user's traffic based on the traffic contracts at the network edge. This work presents a hierarchical traffic shaper implementation which can support a large number of connections with a wide range of connection rates and burstiness without the loss of granularity of the departure time (DT). In contrast to various existing architectures for implementing a traffic shaper, the proposed implementation can reduce cost and complexity greatly by reducing substantial memory size and the number of memory access operations without introducing any sorting inaccuracy.

In this work, through a combination of per-virtual-connection-queue along with two stages of timing queue, we can implement exact sorting with substantial reduced memory size. Meanwhile, by using a look ahead scheme, the proposed shaper architecture can be converted to a near work conserving scheduler. Because we combine the exact sorting algorithm with the accurate departure event driven traffic shaping (DEDTS), there is at most one cell for every connection in sorting unit all the time. So in the proposed shaper scheme, there is no need for a complex arbitration logic unit which reduce the hardware implementation complexity greatly. Through comparing the memory size and the number of memory accesses requirements of proposed architecture with existing architectures, we show that the proposed shaper architecture is more practical in hardware implementation. Through simulation experiments, we demonstrate that the architecture can limit traffic burstiness and support very diverse connection rates with a reduced system.

The proposed hierarchical traffic shaper implementation not only can manage buffer and bandwidth resources effectively in large, high-speed ATM switches, but also can be implemented efficiently with the existing hardware technology. In this project, we use OPNET to construct traffic shaper models, and get a series of simulation results. From these results, we can prove that the proposed traffic shaper have advantage over other existing scheme.

2. Delayed Detection and Its Application in Wireless ATM Networks

A delayed detection protocol and its application in transmitting long compressed files over wireless ATM networks is presented. The protocol is based on a joint source and channel coding automatic repeat request (JARQ) scheme. With this scheme, a special marker character is inserted in the source data periodically before compression. The receiver decompresses packets and checks for the existence of the markers to determine if retransmission is necessary. Since error detection may be delayed, JARQ is applied using a Go-Back-N+M (M>0) protocol. The packet size is analyzed for optimum throughput and a given bit error rate.

Since the optimal packet size varies with the channel condition, a packing scheme, combination or segmentation, of wireless ATM cells based on the calculated optimal packet size is presented. The simulation runs on OPNET. Throughput gain resulted from increasing the code rate is observed.

3. Large Scale Multicast ATM Switch

As a backbone technology for BISDN and Internet, ATM has been under a rapid development in the past 10~15 years. The new class of services, such as teleconferencing and entertainment video, are characterized by high capacity demanding and point-to-multipoint communication. The ever increasing capacity requirements stimulates the enthusiasm in the design and analysis of the ATM switches. It motivates search of effective alternatives for the fundamental issues of multicasting, scalability, and cost-effectiveness in a switching system.

In this paper, we propose a method to approach the desired ATM switch.

Multicast ATM switches allows an incoming cell to be delivered to more than one output port in the switch. Both cell replication and cell routing are very important operations in a multicast ATM switch. Various multicast ATM switches have been proposed in literature.

We study for the design of a large scale multicast ATM switch using input and output link sharing. Switch inputs and outputs are grouped into small modules called Input Shared Blocks (ISBs) and Output Shared blocks (OSBs). Link sharing with round robin cell scheduling solves output contention and eliminates the speedup requirement for the central switch fabric. We introduce two scheduling algorithms which are based on group mapping with round robin from an ISB to an OSB. Both schemes reduce the scheduling complexity dramatically. This switch architecture can be easily extended to a large scale, high speed ATM switch with Terabits capacity.

Simulations for a 256x256 switch is done within OPNET environment. Source model, switch model are generated by three layers processing in OPNET. Parameters are dynamically changed for different switch architecture. Performance analysis indicates a promising performance with 10%~ 15% improved throughput for uniformly distributed non-bursty and bursty multicast traffic.

4. Shared Memory ATM Switch Simulation

An 8x8 shared memory ATM switch has been modeled using OPNET on behalf of a switch manufacturer together with the traffic sources to be use with the shared memory switch. The switch model has been used in simulations to determine several parameters of the switch like EFCI, EPD and PPD thresholds. An explicit rate algorithm for ABR traffic has been implemented and its performance has been simulated and evaluated. UPC and traffic shaping algorithms have been modeled and simulated. Performance of VP tunneling on a UPSR has been simulated.

5. Courses Using OPNET

EE699/CoE681 is a graduate course instructed by Dr. Necdet Uzun. EE699/CoE681 is about Broadband Packet Switches, including switch architecture, performance evaluation, traffic management, switching theory, etc. It provides a view of current broadband network technology like ATM, SONET, Optical Network. With the emphasis on ATM switches, it discusses switch architecture, buffer management, multicasting and traffic control. Projects follows IP switching routers, ATM switches, traffic shaping and scheduling algorithms. OPNET is the recommended simulation environment providing a performance evaluation for network components related with the projects.