CRC Generator Program for GMU CSnets

This version prints CRC with MSB at left.

Enter three characters; this program will append them
to 16 leading bits of zeros representing address and control bytes 
of a HDLC frame, and 16 trailing zeros, and print the resulting 56 bits.

This program will then calculate the 16-bit FCS, using
HDLC protocol specification as defined in Bertsakis & Gallagher,
Data Networks, 2nd Ed. and print that FCS in binary.

Enter three characters:
Your three characters are:123

With 16 leading and 16 trailing zero bits, input in binary is:

00000000000000000011000100110010001100110000000000000000


The HDLC CRC is calculated from this by:
(1) inverting first 16 bits and shifting them into
    CRC register, starting with MSB
(2) shifting more 40 times until all bits have been through
    CRC register (last 16 bits shifted in are zeros);
    each new bit shifted out from MSB of CRC register becomes
    feedback, which is XORed with bits 0, 5 and 12 of CRC register.
(3) after 40th shift, resulting CRC is inverted and shifted out.

Stepping through this process:

(1) CRC register is loaded initially with:0000000000000000

(2) 56 stages of shifting look like this:

Feedback   CRC Bits     Next s

  0    0000000000000000    1
  0    0000000000000001    1
  0    0000000000000011    1
  0    0000000000000111    1
  0    0000000000001111    1
  0    0000000000011111    1
  0    0000000000111111    1
  0    0000000001111111    1
  0    0000000011111111    1
  0    0000000111111111    1
  0    0000001111111111    1
  0    0000011111111111    1
  0    0000111111111111    1
  0    0001111111111111    1
  0    0011111111111111    1
  0    0111111111111111    1
  0    1111111111111111    0
  1    1110111111011111    0
  1    1100111110011111    1
  1    1000111100011110    1
  1    0000111000011100    0
  0    0001110000111000    0
  0    0011100001110000    0
  0    0111000011100000    1
  0    1110000111000001    0
  1    1101001110100011    0
  1    1011011101100111    1
  1    0111111011101110    1
  0    1111110111011101    0
  1    1110101110011011    0
  1    1100011100010111    1
  1    1001111000001110    0
  1    0010110000111101    0
  0    0101100001111010    0
  0    1011000011110100    1
  1    0111000111001000    1
  0    1110001110010001    0
  1    1101011100000011    0
  1    1011111000100111    1
  1    0110110001101110    1
  0    1101100011011101    0
  1    1010000110011011    0
  1    0101001100010111    0
  0    1010011000101110    0
  1    0101110001111101    0
  0    1011100011111010    0
  1    0110000111010101    0
  0    1100001110101010    0
  1    1001011101110101    0
  1    0011111011001011    0
  0    0111110110010110    0
  0    1111101100101100    0
  1    1110011001111001    0
  1    1101110011010011    0
  1    1010100110000111    0
  1    0100001100101111    0
  0    1000011001011110    0

(3) This result is inverted to form the CRC
    (with MSB at left now, the way it is used):0111100110100001